M. Arnold and H. Corporaal, Designing domain-specific processors, In Proc. of the Design, Automation and Test in Europe Conf, 61-66, 2002.
 K. Atasu, L. Pozzi and P. Lenne, Automatic application-specific instruction-set extensions under microarchitectural constraints, In Proc. of the Design, Automation and Test in Europe (DATE), 256-261, 2003.
 F. Barat, R. Lauwereins and G. Deconinck, Reconfigurable instruction set processors from a hardware/software perspective, IEEE Trans. on Software Engineering, vol. 28, no. 9, 847-861, 2002.
 C.Bobda, Synthesis of Dataflow Graphs for Reconfigurable Systems Using Temporal Partitioning and Temporal Placement, Ph.D thesis, University of Paderborn, 2003.
 N. Clark, M. Kudlur, H. Park, S. Mahlke and K. Flautner, Application-specific processing on a general-purpose core via
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Journal of Computer and Robotics 1 (2010) 1-11
transparent instruction set customization, In Proc. of IEEE/ACM Int. Symp. on Microarchitecture, 30-40, 2004.
 M. Karthikeya, P. Gajjala and B. Dinesh, Temporal partitioning and scheduling data flow graphs for reconfigurable computer, IEEE Trans. on Computers, vol. 48, no. 6, 579-590, 1999.
 R. Kastner, A. Kaplan, S. Ogrenci Memik and E. Bozorgzadeh, Instruction generation for hybrid reconfigurable systems, ACM TODAES, vol. 7, no. 4, 605-627, 2002.
 J. Krinke, Identifying Similar Code with Program Dependence Graphs, In Proc. 8th Working Conf. on Reverse Engineering, 301-309, 2001.
 F. Mehdipour, H. Noori, M. Saheb Zamani, K. Murakami, M. Sedighi and K. Inoue, An integrated temporal partitioning and mapping framework for handling custom instructions on a reconfigurable functional unit, The 11th Asia-Pacific Computer Systems Architecture Conf. (ACSAC'06), Lecture Notes in Computer Science, vol. 4186/2006, 219-230, 2006.
 F. Mehdipour, M. Saheb Zamani and M. Sedighi, An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems, Microprocessors and Microsystems, vol. 30, no. 1, 52-62, 2006.
 Mibench. http://www.eecs.umich.edu/mibench.
 G.D. Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.
 H. Noori, F. Mehdipour, K. Murakami, K. Inoue and M. Saheb Zamani, An architecture framework for an adaptive extensible
processor, The Journal of Supercomputing, Springer Netherlands, vol. 45, no. 3, 313-340, 2008.
 I. Ouaiss, S. Govindarajan, V. Srinivasan, M. Kaul and R. Vemuri, An integrated partitioning and synthesis system for dynamically reconfigurable multi-FPGA architectures, In Proc. of the Reconfigurable Architecture Workshop, 31-36, 1998.
 R. Razdan and M.D. Smith, A high-performance microarchitecture with hardware-programmable functional units, In Proc. of the 27th Annual Int. Symp. on Microarchitecture, 172-180, 1994.
 N. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer-Academic Publishers, 1991.
 Simplescalar. http://www.simplescalar.com.
 J. Spillane and H. Owen, Temporal partitioning for partially reconfigurable field programmable gate arrays, IPPS/SPDP Workshops, 37-42, 1998.
 C. Tanougast, Y. Berviller, P. Brunet, S. Weber and H. Rabah, Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system, Microprocessors and Microsystems, vol. 27, 115-130, 2003.
 W.Weisstein,Graphisomorphism,http://mathworld.wolfram.com/ GraphIsomorphism.html.
 Z.A.Ye et al, Chimaera: A high-performance architecture with tightly-coupled reconfigurable functional unit, In Proc. of the 27th Annual Int. Symp. on Computer Architecture, 225-235, 2000.