D. Geer, Chip makers turn to multicore processors, Industry Trends, IEEE Computer Society, pp. 11-13, 2005.
 J. Held, J. Bautista and S. Koehl, From a few cores to many:a tera-scale computing research overview, Intel White Paper, 2006.
 J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer and D. Shippy, Introduction to the cell multiprocessors, IBM Journal of Reserch and Developments, Vol.49, No.4/5, July/Sept. 2005.
 J. L. Hennessy and D. A. Patterson, Computer architecture: a quantitative approach, Morgan-Kaufmann, 4th edition, 2006.
 S.D. Wallace, Scalable Hardware Mechanism for superscalar processors, Ph.D. dissertation, University of California, Irvine, 1997.  M.K. Akbari, M. Shojaei, O. Aghalatifi and B. Javadi, Design and simulation of cache controller unit for a risc processor, 7th Annual CSI Conf. (CSICC 2001), ITRC, Tehran, Iran, 2001.
 K. Skadron and P. S. Ahuja, HydraScalar: A multipath-capable simulator, Newsletter of the IEEE Technical Committee on Computer Architecture, Jan. 2001.
 D. Burger and T. M. Austin, The simplescalar tool set, Version 2.0, Technical Report #1342, University of Wisconsin-Madison Computer Sciences Department, June 1997.
 R. E. Kessler, The Alpha 21264 microprocessor, IEEE Micro, pp. 24-36, Apr.1999.
 G. Reinman and N. Jouppi, An integrated cache timing and power model, Compaq Corp., Western Research Lab., 1999.  M.K. Akbari, B. Javadi, M. Shojaei and O. Aghalatifi, Design and simulation of fetch unit for a RISC processor, 7th Annual CSI Conf. (CSICC 2001), ITRC, Tehran, Iran, 2001.
 Standard Performance Evaluation Corp. SPEC CPU 2000 Benchmarks. http://www.specbench.org, 2000.
 Charles Price, MIPS IV instruction Set, revision 3.1. MIPS Technologies, Inc., M ountain View, CA, Jan. 1995.  M. Shojaei, Design and Simulation of cashe system for a RISC processor with multi-processor capability, MS Thesis, Computre Engineering and Information Technology Department, Amirkabir University of Technology, 2001.
 S. Wallace and N. Bagherzadeh, Instruction fetching mechanism for superscalar microprocessors, Euro-Par'96, Aug. 1996.  B. Javadi, Design and simulation of super-pipelined and super-scalar system for a RISC processor, MS Thesis, Computre Engineering and Information Technology Department, Amirkabir University of Technology, 2001.
 A. N. Eden and T. Mudge, The YAGS branch prediction scheme, Proc. of Micro-31, pp. 69-77, Dec. 1998.
 K. Skadron, M. Martonosi and D. W. Clark, Alloyed global and local branch history: a robust solution to wrong-history mispredictions, Technical Report TR-606-99, Princeton Dept. of Computer Science, 1999.
 K. Skadron, M. Martonosi and D. W. Clark, Alloying global and local branch history: taxonomy, performance, and analysis, Technical Report, Princeton Dept. of Computer Science, 1999.
 W. Burleson, M. Ciesielski, F. Klass and W. Liu, Wave-Pipelining: A tutorial and research survey, IEEE Trans. on VLSI vol.6, no. 3, pp. 464-474, September, 1998.