Soft Error Rate Estimation of Logic Circuits Using Recurrent Neural Networks

Document Type : Original Research (Full Papers)

Authors

1 Computer architecture, Neural Networks

2 Computer Architecture Digital Systems

3 Image Retrieval, Pattern Recognition, Image Mining, Multimedia Databases

Abstract

Nano-scale technology has brought more susceptibility to soft errors for the generation of complicated and state of the art devices. Soft errors are the impacts of radiation of the particles like a neutron, alpha, and ions on the surface of the circuits. To tackle the system malfunctions and provide a reliable device, studying the transient fault effects on the logic circuits can be a more significant issue. This paper presents a new approach based on Recurrent Neural Networks (RNNs) to estimate ICs' Soft Errors Rate (SER). As RNN can be deployed for signal processing and time series, we applied it to investigate transient fault effects while propagating through the combinational and sequential parts of a test chip and compute its SER by simulating and analyzing the circuit outputs. In this paper, the results of utilizing the proposed RNN model to estimate the SER of the ISCAS-85 benchmark circuits have been provided.

Keywords


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  • Receive Date: 09 February 2021
  • Revise Date: 23 February 2021
  • Accept Date: 26 February 2021